EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 2

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
0
Stratix Device Family Data Sheet
Section I–2
Chapter
2
September 2004, v3.1
November 2003, v2.2
October 2003, v2.1
April 2004, v3.0
July 2005 v3.2
Date/Version
Added
Updated
Format changes.
Updated fast regional clock networks description on
Deleted the word preliminary from the “specification for the maximum
time to relock is 100 µs” on
Added information about differential SSTL and HSTL outputs in
“External Clock Outputs” on page
Updated notes in
Added information about m counter to
Division” on page
Updated Note 1 in
Updated description of
page
Updated
Added references to AN 349 and AN 329 to
Interfacing” on page
Table 2–25 on page
4. Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively.
Updated
Added information about PCI Compliance to
Table 2–32 on page
Updated reference to device pin-outs now being available on the web
on
Added Notes 4 and 5 to
Updated Note 3 in
Updated Note 5 in
Added note 3 to rows 11 and 12 in
Deleted “Stratix and Stratix GX Device PLL Availability” table.
Added I/O standards row in
strength.
Row
Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML,
LVDS, and HyperTransport technology rows in
Removed the Left and Right I/O Banks row in
Changed
External RAM Interfacing section replaced.
Added 672-pin BGA package information in
Removed support for series and parallel on-chip termination.
Termination Technology renamed differential on-chip termination.
Updated the number of channels per PLL in Tables 2-38 through 2-
42.
Updated
Updated DDR I information.
Updated
Added
Updated
Updated the Lock Detect section.
page
clk [1,3,8,10]
2–88.
“Clear Signals”
Tables
2–130.
“Power Sequencing & Hot Socketing”
Table 2–22 on page
Table 2–26 on page
Figures 2–65
Table
Figures
RCLK
2–25, 2–29, 2–30, and 2–72.
2–22.
values in
2–59, 2–65, and 2–67.
Figure 2–55 on page
2–101.
Table 2–58 on page
Table 2–37 on page
Table 2–41 on page
2–116: updated the table, updated Notes 3 and
2–126: updated the table and deleted Note 1.
2–115.
section.
and 2–67.
“Clock Multiplication & Division” on
Table 2–36 on page
Changes Made
was removed from
Figures 2–50
page
Table 2–28
2–102.
2–117.
Stratix Device Handbook, Volume 1
2–90.
2–92.
Table
“Clock Multiplication &
2–93.
2–101.
2–131.
2–135.
and 2–51.
that support max and min
2–18.
Table
“External RAM
Table
page
2–130.
Table
Table
section.
Altera Corporation
2–37.
2–30.
2–120.
2–34.
page
2–32.
2–73.