EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 202

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
0
Timing Model
4–32
Stratix Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MRAMBESU
MRAMBEH
MRAMDATAASU
MRAMDATAAH
MRAMADDRASU
MRAMADDRAH
MRAMDATABSU
MRAMDATABH
MRAMADDRBSU
MRAMADDRBH
MRAMDATACO1
MRAMDATACO2
MRAMCLKHL
MRAMCLR
R 4
R 8
R 2 4
C 4
C 8
C 1 6
L O C A L
Table 4–50. M-RAM Block Internal Timing Microparameters (Part 2 of 2)
Table 4–51. Routing Delay Internal Timing Parameters
Symbol
Symbol
Min
-5
1,000
268
371
465
440
577
445
313
Min
135
25
18
25
18
25
18
25
18
25
18
Max
Routing delays vary depending on the load on that specific routing line.
The Quartus II software reports the routing delay information when
running the timing analysis for a design.
-5
1,038
4,362
Max
Min
1,111
-6
Min
150
25
20
25
20
25
20
25
20
25
20
295
349
512
484
634
489
345
Max
-6
1,053
4,939
Max
Min
1,190
Min
172
28
23
28
23
28
23
28
23
28
23
-7
339
401
588
557
730
563
396
Max
-7
1,210
5,678
Max
Min
1,400
Min
202
33
27
33
27
33
27
33
27
33
27
-8
390
461
676
641
840
647
455
Altera Corporation
-8
Max
1,424
6,681
Max
January 2006
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Unit
Unit
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ps
ps
ps
ps
ps
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