EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 235

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

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0
Figure 4–8. Measurement Setup for T
Altera Corporation
January 2006
Notes to
(1)
(2)
(3)
(4)
3.3-V CTT
Table 4–102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 2 of 2)
Notes
Input measurement point at internal node is 0.5 × V
Output measuring point for data is V
rising edge and the other is for the falling edge.
Input stimulus edge rate is 0 to V
The first value is for the output rising edge and the second value is for the output falling edge. The hyphen (-)
indicates infinite resistance or disconnection.
I/O Standard
(1), (2),
Table
CLK
OUT
OUT
4–102:
(3)
R
T
Ω
Figure 4–8
enable timing. The T
same as T
is the same as T
UP
CHZ
T
CLZ
CCINT
R
XZ
Ω
DN
MEAS
and T
XZ
in 0.5 ns (internal signal) from the driver preceding the I/O buffer.
shows the measurement setup for output disable and output
. The T
. When two values are given, the first is the measurement point on the
Loading and Termination
ZX
R
25
Ω
ZX
S
.
CLZ
CHZ
CCINT
50
stands for clock to low Z (driving) time delay and
R
Ω
T
stands for clock to high Z time delay and is the
.
200mV
200mV
200mV
200mV
3.600
V
(V)
CCIO
Stratix Device Handbook, Volume 1
1.650
VTT
(V)
DC & Switching Characteristics
V
(pF)
T
30
C
C
=1.5V
L
TOTAL
R =50
=10pF
Measurement
Ω
V
1.650
Point
MEAS
4–65