EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 238

• Manufacturer Part Number: EP1S30F780I6N
• Description: IC STRATIX FPGA 30K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S30F780I6N

• Number Of Logic Elements/cells: 32470
• Number Of Labs/clbs: 3247
• Total Ram Bits: 3317184
• Number Of I /o: 597
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Timing Model
4–68
Stratix Device Handbook, Volume 1
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
Table 4–105. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)
Parameter
12 mA
24 mA
12 mA
16 mA
24 mA
12 mA
16 mA
12 mA
2 mA
4 mA
8 mA
4 mA
8 mA
2 mA
8 mA
2 mA
8 mA
2 mA
4 mA
8 mA
-5 Speed Grade
Tables 4–105
with column and row I/O pins for both fast and slow slew rates. If an I/O
standard is selected other than 3.3-V LVTTL 4mA or LVCMOS 2 mA with
a fast slew rate, add the selected delay to the external t
t
page 4–36
Min
XZ
, t
ZX
, t
1,895
1,895
1,347
2,517
1,304
6,680
3,275
1,589
1,895
–157
Max
956
189
636
561
834
504
194
960
960
XZPLL
16
50
50
50
50
0
0
9
through
through
, and t
-6 Speed Grade
Min
Table 4–96 on page
ZXPLL
4–108
1,990
1,004
1,990
1,414
2,643
1,369
1,008
1,008
7,014
3,439
1,668
1,990
–165
Max
I/O parameters shown in
198
668
589
875
529
203
17
52
52
52
52
0
0
9
show the output adder delays associated
-7 Speed Grade
Min
4–56.
1,990
1,004
1,990
1,414
2,643
1,369
1,008
1,008
7,014
3,439
1,668
1,990
–165
Max
198
668
589
875
529
203
17
52
52
52
52
0
0
9
-8 Speed Grade
Min
Table 4–55 on
OUTCO
Altera Corporation
1,990
1,004
1,990
1,414
2,643
1,369
1,008
1,008
7,014
3,439
1,668
1,990
–165
January 2006
Max
198
668
589
875
529
203
, t
52
17
52
52
52
0
0
9
OUTCOPLL
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
,