EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 245

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
0
Altera Corporation
January 2006
Note to
(1)
Note to
(1)
Note to
(1)
Drive Strength
VCCIO Voltage
Level
Table 4–111. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers
Table 4–112. Output Delay Adder for Loading on SSTL/HSTL Output Buffers
Table 4–113. Output Delay Adder for Loading on GTL+/GTL/CTT/PCI Output Buffers
Parameter
Parameter
The timing information in this table is preliminary.
The timing information in this table is preliminary.
The timing information in this table is preliminary.
Table
Table
Table
Conditions
Class II
Conditions
Class I
Conditions
4–111:
4–112:
4–113:
Value
3.3V
2.5V
Value
24mA
16mA
12mA
8mA
4mA
2mA
The scaling factors for column output pin timing in
are shown in units of time per pF unit of capacitance (ps/pF). Add this
delay to the t
pins in addition to the I/O adder delays shown in
4–108
3.3-V LVTTL
SSTL-3
and the IOE programmable delays in
GTL+
25
25
18
15
15
25
30
50
60
CO
or combinatorial timing path for output or bidirectional
2.5-V LVTTL
Output Pin Adder Delay (ps/pF)
GTL
18
18
Output Pin Adder Delay (ps/pF)
SSTL-2
Output Pin Adder Delay (ps/pF)
18
25
35
75
25
20
1.8-V LVTTL
CTT
120
25
25
40
-
Stratix Device Handbook, Volume 1
SSTL-1.8
DC & Switching Characteristics
25
25
Tables 4–109
Note (1)
1.5-V LVTTL
Note (1)
Tables 4–103
160
Tables 4–111
PCI
35
80
20
-
-
Note (1)
and 4–110.
1.5-V HSTL
25
20
LVCMOS
through
to
AGP
15
20
30
60
8
20
-
4–113
4–75