EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 265

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
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Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
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Part Number:
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Manufacturer:
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0
Altera Corporation
January 2006
t
f
% spread
t
t
F I G
f
f
f
f
t
t
t
f
f
t
t
t
t
SKEW
SS
ARESET
A R E S E T _ R E C O N
IN
INPFD
INDUTY
EINDUTY
INJITTER
EINJITTER
FCOMP
OUT
OUT_EXT
OUTDUTY
JITTER
CONFIG5,6
CONFIG11,12
Table 4–127. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2)
Table 4–128. Enhanced PLL Specifications for -6 Speed Grades
Symbol
Symbol
Input clock frequency
Input frequency to PFD
Input clock duty cycle
External feedback clock input duty
cycle
Input clock period jitter
External feedback clock period jitter
External feedback clock compensation
time
Output frequency for internal global or
regional clock
Output frequency for external clock
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
(6)
Time required to reconfigure the scan
chains for PLLs 5 and 6
Time required to reconfigure the scan
chains for PLLs 11 and 12
(4)
Clock skew between two external
clock outputs driven by the different
counters with the same settings
Spread spectrum modulation
frequency
Percentage spread for spread
spectrum frequency
Minimum pulse width on
signal
Minimum pulse width on the
areset
reconfiguration. Reset the PLL after
scandataout
Parameter
signal when using PLL
Parameter
goes high.
(10)
areset
(3)
(1),
Min
0.3
0.3
40
40
45
3
3
(2)
Min
500
0.4
30
10
Typ
±75
Typ
0.5
±20 mUI for <200-MHz outclk
±100 ps for >200-MHz outclk
(Part 1 of 2)
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
289/f
193/f
±200
±200
Max
650
420
450
500
60
60
55
SCANCLK
SCANCLK
6
Max
150
0.6
(3)
(3)
ps or
MHz
MHz
MHz
MHz
Unit
mUI
Unit
kHz
ps
ps
ns
%
%
%
ps
ns
ns
4–95
%