EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 28
Manufacturer Part Number
IC STRATIX FPGA 30K LE 780-FBGA
Specifications of EP1S30F780I6N
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Voltage - Supply
1.425 V ~ 1.575 V
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
Stratix Device Handbook, Volume 1
asynchronous load, and clear signals. An asynchronous clear signal takes
precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one preset signal.
In addition to the clear and preset ports, Stratix devices provide a chip-
wide reset pin (DEV_CLRn) that resets all registers in the device. An
option set before compilation in the Quartus II software controls this pin.
This chip-wide reset overrides all other control signals.
In the Stratix architecture, connections between LEs, TriMatrix memory,
DSP blocks, and device I/O pins are provided by the MultiTrack
interconnect structure with DirectDrive
interconnect consists of continuous, performance-optimized routing lines
of different lengths and speeds used for inter- and intra-design block
connectivity. The Quartus II Compiler automatically places critical design
paths on faster interconnects to improve design performance.
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
within the device. The MultiTrack interconnect and DirectDrive
technology simplify the integration stage of block-based designing by
eliminating the re-optimization cycles that typically follow design
changes and additions.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and repeatable performance when
migrating through different device densities. Dedicated row
interconnects route signals to and from LABs, DSP blocks, and TriMatrix
memory within the same row. These row resources include:
The direct link interconnect allows an LAB, DSP block, or TriMatrix
memory block to drive into the local interconnect of its left and right
neighbors and then back into itself. Only one side of a M-RAM block
interfaces with direct link and row interconnects. This provides fast
communication between adjacent LABs and/or blocks without using row
The R4 interconnects span four LABs, three LABs and one M512 RAM
block, two LABs and one M4K RAM block, or two LABs and one DSP
block to the right or left of a source LAB. These resources are used for fast
Direct link interconnects between LABs and adjacent blocks.
R4 interconnects traversing four blocks to the right or left.
R8 interconnects traversing eight blocks to the right or left.
R24 row interconnects for high-speed access across the length of the
technology. The MultiTrack