EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 36

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
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Part Number:
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Manufacturer:
ALTERA
0
TriMatrix Memory
2–22
Stratix Device Handbook, Volume 1
1
Memory Modes
TriMatrix memory blocks include input registers that synchronize writes
and output registers to pipeline designs and improve system
performance. M4K and M-RAM memory blocks offer a true dual-port
mode to support any combination of two-port operations: two reads, two
writes, or one read and one write at two different clock frequencies.
Figure 2–12
Figure 2–12. True Dual-Port Memory Configuration
Notes to
(1)
(2)
Configurations
Table 2–3. TriMatrix Memory Features (Part 2 of 2)
Memory Feature
See
The M-RAM block does not support memory initializations. However, the
M-RAM block can emulate a ROM function using a dual-port RAM bock. The
Stratix device must write to the dual-port memory once and then disable the
write-enable ports afterwards.
Table 4–36
Table
Violating the setup or hold time on the address registers could
corrupt the memory contents. This applies to both read and
write operations.
shows true dual-port memory.
2–3:
for maximum performance information.
data
address
wren
clocken
q
aclr
A
clock
[ ]
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
A
M512 RAM Block
A
A
[ ]
(32 × 18 Bits)
A
A
A
[ ]
A
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
M4K RAM Block
(128 × 36 Bits)
B
address
clocken
clock
data
wren
aclr
q
B
B
B
B
[ ]
[ ]
[ ]
B
B
B
Altera Corporation
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
(4K × 144 Bits)
M-RAM Block
July 2005