EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 49

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
0
Altera Corporation
July 2005
The read and write operation of the memory is controlled by the WREN
signal, which sets the ports into either read or write modes. There is no
separate read enable (RE) signal.
Writing into RAM is controlled by both the WREN and byte enable
(byteena) signals for each port. The default value for the byteena
signal is high, in which case writing is controlled only by the WREN signal.
The byte enables are available for the ×18, ×36, and ×72 modes. In the
×144 simple dual-port mode, the two sets of byteena signals
(byteena_a and byteena_b) are combined to form the necessary
16 byte enables.
64K
32K
16K
8K
Table 2–9. M-RAM Block Configurations (True Dual-Port)
Table 2–10. Byte Enable for M-RAM Blocks
byteena[3..0]
×
×
×
×
72
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
9
18
36
Port A
Tables 2–10
datain ×18
[17..9]
64K × 9
[8..0]
v
v
v
v
and
2–11
32K × 18
summarize the byte selection.
Stratix Device Handbook, Volume 1
v
v
v
v
datain ×36
Notes
[26..18]
[35..27]
[17..9]
[8..0]
Port B
(1),
16K × 36
(2)
v
v
v
v
Stratix Architecture
datain ×72
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
[17..9]
[8..0]
8K × 72
v
v
v
v
2–35