EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 52

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
TriMatrix Memory
Figure 2–20. EP1S60 Device with M-RAM Interface Locations
Note to
(1)
2–38
Stratix Device Handbook, Volume 1
Device shown is an EP1S60 device. The number and position of M-RAM blocks varies in other devices.
Figure
Blocks
DSP
2–20:
Blocks
top, bottom, and side opposite
M512
M-RAM
M-RAM
M-RAM pairs interface to
of block-to-block border.
Block
Block
The M-RAM block local interconnect is driven by the R4, R8, C4, C8, and
direct link interconnects from adjacent LABs. For independent M-RAM
blocks, up to 10 direct link address and control signal input connections
to the M-RAM block are possible from the left adjacent LABs for M-RAM
M-RAM
M-RAM
Block
Block
Blocks
M4K
Note (1)
LABs
interface to top, bottom, and side facing
device perimeter for easy access
M-RAM
M-RAM
Independent M-RAM blocks
Block
Block
to horizontal I/O pins.
Altera Corporation
Blocks
DSP
July 2005