EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 84

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
Digital Signal Processing Block
2–70
Stratix Device Handbook, Volume 1
Note to
(1)
Multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
Table 2–16. Multiplier Size & Configurations per DSP block
The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned
implementations.
DSP Block Mode
Table
2–16:
For FIR filters, the DSP block combines the four-multipliers adder mode
with the shift register inputs. One set of shift inputs contains the filter
data, while the other holds the coefficients loaded in serial or parallel. The
input shift register eliminates the need for shift registers external to the
DSP block (i.e., implemented in LEs). This architecture simplifies filter
design since the DSP block implements all of the filter circuitry.
One DSP block can implement an entire 18-bit FIR filter with up to four
taps. For FIR filters larger than four taps, DSP blocks can be cascaded with
additional adder stages implemented in LEs.
Table 2–16
DSP block mode according to size. These modes allow the DSP blocks to
implement numerous applications for DSP including FFTs, complex FIR,
FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication
and many other functions.
DSP Block Interface
Stratix device DSP block outputs can cascade down within the same DSP
block column. Dedicated connections between DSP blocks provide fast
connections between the shift register inputs to cascade the shift register
chains. You can cascade DSP blocks for 9 × 9- or 18 × 18-bit FIR filters
larger than four taps, with additional adder stages implemented in LEs.
If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or
accumulator stages are implemented in LEs. Each DSP block can route the
shift register chain out of the block to cascade two full columns of DSP
blocks.
Eight multipliers with
eight product outputs
Two multiply and
accumulate (52 bits)
Four sums of two
multiplier products each
Two sums of four
multiplier products each
9 × 9
shows the different number of multipliers possible in each
Four multipliers with four
product outputs
Two multiply and
accumulate (52 bits)
Two sums of two
multiplier products each
One sum of four multiplier
products each
18 × 18
One multiplier with one
product output
Altera Corporation
36 × 36
(1)
July 2005