EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 92

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
PLLs & Clock Networks
2–78
Stratix Device Handbook, Volume 1
Figure 2–45. EP1S30 Device Fast Regional Clock Pin Connections to Fast
Regional Clocks
Notes to
(1)
(2)
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources
consisting of 16 global clock lines, four regional clock lines, and two fast
regional clock lines. Multiplexers are used with these clocks to form eight
bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer is used at the LAB level to select two of the eight row
clocks to feed the LE registers within the LAB. See
This is a set of two multiplexers.
In addition to the FCLK pin inputs, there is also an input from the I/O interconnect.
(1), (2)
(1), (2)
Figure
FCLK3
FCLK1
2–45:
FCLK0
FCLK2
(1), (2)
(1), (2)
(1), (2)
(1), (2)
FCLK7
FCLK5
FCLK6
FCLK4
(1), (2)
(1), (2)
Figure
Altera Corporation
2–46.
fclk[1..0]
July 2005