EP2SGX90EF1152C5N Altera, EP2SGX90EF1152C5N Datasheet - Page 149
EP2SGX90EF1152C5N
Manufacturer Part Number
EP2SGX90EF1152C5N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C5N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1768
EP2SGX90EF35C5NES
EP2SGX90EF35C5NES
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Figure 2–90. Fast PLL and Channel Layout in the EP2SGX30C/D and EP2SGX60C/D Devices
Note to
(1)
Altera Corporation
October 2007
See
Figure
Table 2–38
2–90:
4
for the number of channels each device supports.
2
2
4
4
For high-speed source synchronous interfaces such as POS-PHY 4 and the
Parallel RapidIO standard, the source synchronous clock rate is not a
byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols because the source synchronous clock does
not provide a byte or word boundary since the clock is one half the data
rate, not one eighth. The Stratix II GX device’s high-speed differential I/O
circuitry provides dedicated data realignment circuitry for
user-controlled byte boundary shifting. This simplifies designs while
saving ALM resources. You can use an ALM-based state machine to
signal the shift of receiver byte boundaries until a specified pattern is
detected to indicate byte alignment.
Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left side of the device has one receiver channel and one
transmitter channel per LAB row.
channel layout in the EP2SGX30C/D and EP2SGX60C/D devices.
Figure 2–91
EP2SGX90E/F, and EP2SGX130G devices.
PLL 1
PLL 2
Fast
Fast
LVDS
LVDS
Clock
Clock
shows the fast PLL and channel layout in EP2SGX60E,
Clock
Clock
DPA
DPA
Quadrant
Quadrant
Stratix II GX Device Handbook, Volume 1
Figure 2–90
shows the fast PLL and
Quadrant
Quadrant
Stratix II GX Architecture
Note (1)
2–141
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