EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 23
EP2SGX90EF1152C4N
Manufacturer Part Number
EP2SGX90EF1152C4N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C4N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1767
EP2SGX90EF35C4NES
EP2SGX90EF35C4NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX90EF1152C4N
Manufacturer:
ALTERA
Quantity:
648
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Altera Corporation
October 2007
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Receiver Input Buffer
The Stratix II GX receiver input buffer supports the 1.2-V and 1.5-V
PCML I/O standard at rates up to 6.375 Gbps. The common mode voltage
of the receiver input buffer is programmable between 0.85 V and 1.2 V.
You must select the 0.85 V common mode voltage for AC- and
DC-coupled PCML links and the 1.2 V common mode voltage for
DC-coupled LVDS links.
The receiver has programmable on-chip 100-, 120-, or 150-Ω differential
termination for different protocols, as shown in
receiver’s internal termination can be disabled if external terminations
and biasing are provided. The receiver and transmitter differential
termination resistances can be set independently of each other.
Figure 2–12. Receiver Input Buffer
Programmable Termination
The programmable termination can be statically set in the Quartus II
software.
termination. The termination can be disabled if external termination is
provided.
Input
Pins
Lane deskew
Rate matcher
8B/10B decoder
Byte deserializer
Byte ordering
Receiver phase compensation FIFO buffer
Figure 2–13
Programmable
Termination
shows the setup for programmable receiver
Stratix II GX Device Handbook, Volume 1
Programmable
Equalizer
Figure
Stratix II GX Architecture
2–12. The
Differential
Buffer
Input
2–15
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