EP2S130F1020C4 Altera, EP2S130F1020C4 Datasheet - Page 79
EP2S130F1020C4
Manufacturer Part Number
EP2S130F1020C4
Description
IC STRATIX II FPGA 130K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F1020C4
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
742
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1413
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F1020C4
Manufacturer:
ALTERA
Quantity:
748
Part Number:
EP2S130F1020C4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2S130F1020C4N
Manufacturer:
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Quantity:
1 730
Company:
Part Number:
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Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S130F1020C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–46. Stratix II IOE Structure
Altera Corporation
May 2007
Logic Array
Output B
Output A
Input B
Input A
OE
Output Register
Output Register
The IOEs are located in I/O blocks around the periphery of the Stratix II
device. There are up to four IOEs per row I/O block and four IOEs per
column I/O block. The row I/O blocks drive row, column, or direct link
interconnects. The column I/O blocks drive column interconnects.
Figure 2–47
Figure 2–48
D
D
Q
Q
shows how a row I/O block connects to the logic array.
shows how a column I/O block connects to the logic array.
CLK
OE Register
OE Register
D
D
Q
Q
Stratix II Device Handbook, Volume 1
Input Register
Input Register
D
D
Q
Q
Input Latch
D
ENA
Stratix II Architecture
Q
2–71