EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 1036
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- Current page: 1036 of 1154
- Download datasheet (32Mb)
2–18
Table 2–3. Device Specific Parameters
Table 2–4. Configuring the Transceiver
Stratix IV Device Handbook Volume 3
Do the parameters meet the fibre channel protocol
electrical requirements?
Are three transceiver channels available?
Is there support for 4.25 Gbps and 1.0625 Gbps data
rates?
Is the 8B/10B encoder in the PCS block fibre channel
compliant?
Is there a workaround?
Is the clock rate compensation block in the PCS available
without an 8B/10B encoder?
Phase 1—Architecture
f
In this phase, check whether the Stratix IV GX device supports or meets your design
requirements.
Device Specification
Consider the questions listed in
For the maximum data rates supported, refer to the “Transceiver Performance
Specifications” section in the
chapter.
Transceiver Configuration
The fibre channel protocol uses an 8B/10B encoder and requires clock rate
compensation.
Functional Blocks
Consider the questions listed in
Questions
Questions
DC and Switching Characteristics for Stratix IV Devices
No
The fibre channel protocol consists of two different
End-of-Frame (EOFt) ordered sets. The correct EOFt ordered
set sent by the user logic depends on the ending disparity of
the word preceeding the EOFt. The Stratix IV GX transceiver
does not provide running disparity flags to the user logic.
Therefore, the user logic might not be able to select the
correct EOFt ordered set.
Yes
Implement the 8B/10B encoder in the FPGA fabric.
No
You can implement this in the FPGA fabric.
Yes
For more information, refer to the “Transceiver Performance
Characteristics” section in the
Characteristics for Stratix IV Devices
Yes
Yes
Two CMU PLLs are available within each transceiver block to
support two different transmitter data rates. Each receiver
channel contains a dedicated receiver CDR that supports
4.25 Gbps and 1.0625 Gbps data rates.
Table 2–3
Table 2–4
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
before setting device-specific parameters.
before configuring the transceiver.
Example 1: Fibre Channel Protocol Application
Answer
Answer
DC and Switching
February 2011 Altera Corporation
chapter
Related parts for EP4SGX290KF40C3N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: