EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 1126
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Core Performance Specifications
f
1
Transceiver Datapath PCS Latency
For more information about:
■
■
■
■
■
■
■
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), TriMatrix, configuration, JTAG, and chip-wide reset (Dev_CLRn)
specifications.
Clock Tree Specifications
Table 1–33
Table 1–33. Clock Tree Performance for Stratix IV Devices—Preliminary
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
Global clock and
Regional clock
Periphery clock
Basic mode PCS latency, refer to Figure 1-90 through Figure 1-97 in the
Architecture in Stratix IV Devices
PCIe mode PCS latency, refer to Figure 1-102 in the
Stratix IV Devices
XAUI mode PCS latency, refer to Figure 1-119 in the
Stratix IV Devices
GIGE mode PCS latency, refer to Figure 1-128 in the
Stratix IV Devices
SONET/SDH mode PCS latency, refer to Figure 1-136 in the
Architecture in Stratix IV Devices
SDI mode PCS latency, refer to Figure 1-141 in the
Stratix IV Devices
(OIF) CEI PHY mode PCS latency, refer to Figure 1-143 in the
Architecture in Stratix IV Devices
Symbol
lists the clock tree specifications for Stratix IV devices.
–2/–2× Speed Grade
chapter.
chapter.
chapter.
chapter.
800
550
Performance
chapter.
chapter.
chapter.
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
–3 Speed Grade
700
500
Transceiver Architecture in
Transceiver Architecture in
Transceiver Architecture in
Transceiver Architecture in
–4 Speed Grade
April 2011 Altera Corporation
Transceiver
500
450
Transceiver
Switching Characteristics
Transceiver
Unit
MHz
MHz
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