EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 600
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–156
Figure 1–123. Stratix IV GX and GT XAUI Mode Configuration
Stratix IV Device Handbook Volume 2: Transceivers
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
Interface Frequency
PMA-PCS Interface
Fabric-Transceiver
Encoder/Decoder
Fabric-Transceiver
TX PCS Latency
Interface Frequency
Functional Modes
Low-Latency PCS
RX PCS Latency
Channel Bonding
Data Rate (Gbps)
Rate Match FIFO
Functional Mode
Deskew FIFO
(Pattern Length)
Byte Ordering
Interface Width
Byte SerDes
Word Aligner
8B/10B
FPGA
(MHz)
Width
FPGA
Figure 1–123
devices.
8-bit
Single
Width
10-bit
shows the XAUI mode configuration supported in Stratix IV GX and GT
Basic
16-bit
Double
Width
Stratix IV GX and GT Configurations
20-bit
10-bit
PIPE
10-bit
XAUI
Synchronization
(10-Bit/K28.5/)
State Machine
3.125 - 3.75
Automatic
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
XAUI
156.25-
16-Bit
187.5
4.5 - 6
14.5 -
GIGE
10-bit
x4
Chapter 1: Transceiver Architecture in Stratix IV Devices
18
Protocol
SRIO
10-bit
SONET
/SDH
8-bit
16-bit
(OIF)
CEI
February 2011 Altera Corporation
Transceiver Block Architecture
10-bit
SDI
10-Bit
Deterministic
Latency
20-Bit
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