EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 654
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–210
Table 1–73. Stratix IV GX and GT ALTGX Megafunction Ports: Transmitter Ports (Part 2 of 3)
Stratix IV Device Handbook Volume 2: Transceivers
8B/10B Encoder
tx_ctrlenable
tx_forcedisp
tx_dispval
Port Name
Output
Input/
Input
Input
Input
pulse width is two
pulse width is two
signal. Minimum
signal. Minimum
Synchronous to
Asynchronous
Asynchronous
Clock Domain
parallel clock
parallel clock
tx_clkout/
coreclkout
clock signal.
cycles.
cycles.
8B/10B encoder /Kx.y/ or /Dx.y/ control.
■
■
■
8B/10B encoder force disparity control.
■
■
■
8B/10B encoder force disparity value.
■
■
■
When asserted high—the 8B/10B encoder
encodes the data on the tx_datain port as
a /Kx.y/ control code group.
When de-asserted low—it encodes the data
on the tx_datain port as a /Dx.y/ data code
group.
Channel Width:
8—tx_ctrlenable = 1
16—tx_ctrlenable = 2
32—tx_ctrlenable = 4
When asserted high—forces the 8B/10B
encoder to encode the data on the
tx_datain port with a positive or negative
disparity depending on the tx_dispval
signal level.
When de-asserted low—the 8B/10B encoder
encodes the data on the tx_datain port
according to the 8B/10B running disparity
rules.
Channel Width:
8—tx_forcedisp = 1
16—tx_forcedisp = 2
32—tx_forcedisp = 4
A high level—when the tx_forcedisp
signal is asserted high, it forces the 8B/10B
encoder to encode the data on the
tx_datain port with a negative starting
running disparity.
A low level—when the tx_forcedisp
signal is asserted high, it forces the 8B/10B
encoder to encode the data on the
tx_datain port with a positive starting
running disparity.
Channel Width:
8—tx_dispval = 1
16—tx_dispval = 2
32—tx_dispval = 4
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
February 2011 Altera Corporation
Transceiver Port Lists
Channel
Channel
Channel
Scope
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