EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 836
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
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Manufacturer
Quantity
Price
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4–30
Figure 4–17. Reset Sequence with CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) For t
Stratix IV Device Handbook Volume 2: Transceivers
Figure
pll_powerdown
LTR_LTD_Manual
LTD_Manual
Reset and Power Down Signals
4–17:
duration, refer to the
duration, refer to the
duration, refer to the
Ouput Status Signals
CDR Control Signals
rx_analogreset[0]
rx_analogreset[3]
Receiver and Transmitter Channel Set-up—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. For PMA Direct
drive ×N mode, with receiver CDR in manual lock mode, use the reset sequence
shown in
pll_powerdown
rx_locktorefclk[3]
rx_locktorefclk[0]
rx_dataout[63:0]
rx_locktodata[0]
rx_locktodata[3]
rx_pll_locked[0]
rx_pll_locked[3]
pll_locked
busy
DC and Switching Characteristics for Stratix IV Devices
Figure
DC and Switching Characteristics for Stratix IV Devices
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
4–17. In this example, N = 4.
2
3
Minimum of Two Parallel Clock Cycles
4
5
5
t
6
6
LTR_LTD_Manual (2)
Chapter 4: Reset Control and Power Down in Stratix IV Devices
7
7
7
7
t
LTD_Manual (3)
chapter.
chapter.
chapter.
8
PMA Direct Drive Mode Reset Sequences
valid parallel data into FPGA fabric
February 2011 Altera Corporation
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