XC3SD1800A-5CS484C Xilinx Inc, XC3SD1800A-5CS484C Datasheet - Page 34
![SPARTAN-3ADSP FPGA 1800K 484CSA](/photos/6/73/67348/pk223-cs484_sml.jpg)
XC3SD1800A-5CS484C
Manufacturer Part Number
XC3SD1800A-5CS484C
Description
SPARTAN-3ADSP FPGA 1800K 484CSA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-5CS484C
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Total Ram Bits
1548288
Number Of I /o
309
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA, CSPBGA
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-5CS484C
Manufacturer:
XILINX
Quantity:
648
Part Number:
XC3SD1800A-5CS484C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (V
with the parameters used in
not confuse V
model with V
table. A fourth parameter, C
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
2. Record the time to V
3. Simulate the same signal standard with the output
4. Record the time to V
5. Compare the results of steps 2 and 4. Add (or subtract)
Simultaneously Switching Output
Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the V
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
DS610 (v3.0) October 4, 2010
Product Specification
www.xilinx.com/support/download/index.htm
driver connected to the test setup shown in
Use parameter values V
C
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including V
and V
load.
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment
yield the worst-case delay of the PCB trace.
REF
is zero.
MEAS
REF
REF
REF
values) or capacitive value to represent the
, R
(the input-switching threshold) from the
(the termination voltage) from the IBIS
REF
, and V
M
MEAS
.
REF
T
Table 26
, R
.
MEAS
, is always zero. The four
T
, and V
) correspond directly
(V
REF
T
M
, R
from
, R
T
, and V
(Table
REF
Table
Figure
, C
M
25) to
REF
CCO
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
). Do
26.
www.xilinx.com
8.
,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Table 27
guidelines. For each device/package combination,
provides the number of equivalent V
equivalent number of pairs is based on characterization and
may not match the physical number of pairs. For each
output signal standard and drive strength,
recommends the maximum number of SSOs, switching in
the same direction, allowed per V
I/O bank. The guidelines in
package style, slew rate, and output drive current.
Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3)
support higher output drive current.
Multiply the appropriate numbers from
Table 28
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The SSO values assume that the V
3.3V. Setting V
characteristics.
Table 27: Equivalent V
XC3SD1800A
XC3SD3400A
SSO
Device
MAX
and
to calculate the maximum number of SSOs
/IO Bank =
Table 28
CCAUX
to 2.5V provides better SSO
provide the essential SSO
Package Style (including Pb-free)
Table 27
CCO
CS484
Table 28
/GND Pairs per Bank
6
6
CCO
x
Table 28
CCAUX
CCO
are categorized by
/GND pair within an
Table 27
/GND pairs. The
is powered at
Table 28
FG676
and
10
9
Table 27
34