XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 103
![no-image](/images/no-image-200.jpg)
XC4VFX12-10SFG363C
Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Reset (RST) and Release (REL) Control Signals
R
RST and REL are the control signals for the PMCD. The interaction between RST, REL, and
the PMCD input clocks help manage the starting and stopping of PMCD outputs.
The reset (RST) signal affects the PMCD clock outputs in the following manner:
•
•
•
Asserting RST asynchronously forces all outputs Low.
Deasserting RST synchronously allows all outputs to toggle:
♦
♦
♦
By setting the RST_DEASSERT_CLK attribute, deasserting RST can be synchronized
to any of the four input clocks. The default value of RST_DEASSERT_CLK is CLKA
(see
The delayed outputs begin toggling one cycle after RST is deasserted and is
registered.
If EN_REL = FALSE (default), the divided outputs will also begin toggling one
cycle after RST is deasserted and is registered.
If EN_REL = TRUE, then a positive edge on REL starts the divided outputs
toggling on the next positive edge of CLKA.
Table
CLKA1D2
CLKA1D4
CLKA1D8
CLKC1
CLKD1
CLKA1
CLKB1
CLKC
CLKD
CLKA
CLKB
3-3).
www.xilinx.com
Figure 3-4: Matched Clock Phase
T
PMCCKO_CLKIN
PMCD Usage and Design Guidelines
ug070_3_04_071404
103
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