XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 331
![no-image](/images/no-image-200.jpg)
XC4VFX12-10SFG363C
Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Input Delay Element (IDELAY)
R
Table 7-5
in the
Table 7-5: ILOGIC Switching Characteristics
Every ILOGIC block contains a programmable absolute delay element called IDELAY.
(Refer to
element with a fixed, guaranteed tap resolution (see
to the combinatorial input path, registered input path, or both. IDELAY allows incoming
signals to be delayed on an individual basis. The delay element is calibrated to provide an
absolute delay value (T
temperature variation. Three modes of operation are available:
Setup/Hold
T
T
T
T
T
T
T
Combinatorial
T
T
Sequential Delays
T
T
T
T
T
ICE1CK
ICECK
IRSTCK
IINCCK
ISRCK
IDOCK
IDOCKD
IDI
IDID
IDLO
IDLOD
ICKQ
ICE1Q
RQ
Virtex-4 Data
Symbol
/T
/T
/T
/T
/T
/T
Figure
describes the function and control signals of the ILOGIC switching characteristics
/T
ICKSR
ICKCE
IOCKD
ICKCE1
ICKRST
ICKINC
IOCKDD
7-1,
Sheet.
“ILOGIC Block
CE1 pin setup/hold with respect to CLK
DLYCE pin setup/hold with respect to CLKDIV
DLYRST pin setup/hold with respect to CLKDIV
DLYINC pin setup/hold with respect to CLKDIV
SR/REV pin setup/hold with respect to CLK
D pin setup/hold with respect to CLK without Delay
D pin setup/hold with respect to CLK
(IOBDELAY_TYPE = DEFAULT)
D pin setup/hold with respect to CLK
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin to O pin propagation delay, no Delay
D pin to O pin propagation delay (IOBDELAY_TYPE = DEFAULT)
D pin to O pin propagation delay
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin to Q1 pin using flip-flop as a latch without Delay
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = DEFAULT)
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
CLK to Q outputs
CE1 pin to Q1 using flip-flop as a latch, propagation delay
SR/REV pin to OQ/TQ out
IDELAYRESOLUTION
www.xilinx.com
Diagram.”) IDELAY is a 64-tap wrap-around delay
) independent of process, voltage, and
Description
Virtex-4 Data
Sheet). It can be applied
ILOGIC Resources
331
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