XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 48
![no-image](/images/no-image-200.jpg)
XC4VFX12-10SFG363C
Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 1: Clock Resources
48
BUFGCE and BUFGCE_1 VHDL and Verilog Templates
Verilog Template
Declaring Constraints in UCF File
VHDL Template
The following examples illustrate the instantiation of the BUFGCE module in VHDL and
Verilog. The instantiation of BUFGCE_1 is exactly the same as BUFGCE with exception of
the primitive name.
//Example BUFG module declaration
module BUFG (O, I);
endmodule;
//Example BUFG instantiation
BUFG U_BUFG (
.O(user_o),
.I0(user_i)
);
// Declaring constraints in Verilog
// synthesis attribute LOC of U_BUFG is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
INST "U_BUFG" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
--Example BUFGCE declaration
component BUFGCE
port(
end component;
--Example BUFGCE instantiation
U_BUFGCE : BUFGCE
Port map (
--Declaring constraints in VHDL file
attribute LOC : string;
attribute LOC of U_BUFGCE: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
output O;
input I;
O: out std_ulogic;
CE: in
I: in
);
O => user_o,
CE => user_ce,
I => user_i
);
std_ulogic
std_ulogic;
www.xilinx.com
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R
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