XC4VFX12-11SFG363I Xilinx Inc, XC4VFX12-11SFG363I Datasheet - Page 217
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XC4VFX12-11SFG363I
Manufacturer Part Number
XC4VFX12-11SFG363I
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-11SFG363I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
363-FBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
VHDL and Verilog Instantiations
Port Signals
R
Clock - WCLK
Enable - WE
Address - A0, A1, A2, A3 (A4, A5)
Data In - D
Data Out - O, SPO, and DPO
Inverting Control Pins
Global Set/Reset - GSR
VHDL and Verilog instantiation templates are available as examples (see
Verilog
In VHDL, each template has a component declaration section and an architecture section.
Each part of the template should be inserted within the VHDL design file. The port map of
the architecture section should include the design signal names.
The RAM_#S templates (with # = 16, 32, 64) are single-port modules and instantiate the
corresponding RAM#X1S primitive.
RAM_16D templates are dual-port modules and instantiate the corresponding
RAM16X1D primitive.
Each distributed RAM port operates independently of the other while reading the same set
of memory cells.
The clock is used for the synchronous write. The data and the address input pins have
setup time referenced to the WCLK pin.
The enable pin affects the write functionality of the port. An inactive Write Enable prevents
any writing to memory cells. An active Write Enable causes the clock edge to write the data
input signal to the memory location pointed to by the address inputs.
The address inputs select the memory cells for read or write. The width of the port
determines the required address inputs. Note that the address inputs are not a bus in
VHDL or Verilog instantiations.
The data input provides the new data value to be written into the RAM.
The data out O (Single-Port or SPO) and DPO (Dual-Port) reflects the contents of the
memory cells referenced by the address inputs. Following an active write clock edge, the
data out (O or SPO) reflects the newly written data.
The two control pins (WCLK and WE) each have an individual inversion option. Any
control signal, including the clock, can be active at 0 (negative edge for the clock) or at 1
(positive edge for the clock) without requiring other logic resources.
The global set/reset (GSR) signal does not affect distributed RAM modules. For more
information on the GSR, see the BUFGSR section in the Xilinx Software Manual.
Templates).
www.xilinx.com
CLB Primitives and Verilog/VHDL Examples
VHDL and
217
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