XC4VFX12-11FFG668I Xilinx Inc, XC4VFX12-11FFG668I Datasheet - Page 99
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XC4VFX12-11FFG668I
Manufacturer Part Number
XC4VFX12-11FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-11FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Phase-Matched Clock Dividers
(PMCDs)
PMCD Summary
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
The Phase-Matched Clock Dividers (PMCDs) are one of the clock resources available in the
Virtex-4 architecture. PMCDs provide the following clock management features:
•
•
Phase-Matched Divided Clocks
The PMCDs create up to four frequency-divided and phase-matched versions of an
input clock, CLKA. The output clocks are a function of the input clock frequency:
divided-by-1 (CLKA1), divided-by-2 (CLKA1D2), divided-by-4 (CLKA1D4), and
divided-by-8 (CLKA1D8). CLKA1, CLKA1D2, CLKA1D4, and CLKA1D8 output
clocks are rising-edge aligned to each other but not to the input (CLKA).
Phase-Matched Delay Clocks
PMCDs preserve edge alignments, phase relations, or skews between the input clock
CLKA and other PMCD input clocks. Three additional inputs (CLKB, CLKC, and
CLKD) and three corresponding delayed outputs (CLKB1, CLKC1, and CLKD1) are
available. The same delay is inserted to CLKA, CLKB, CLKC, and CLKD; thus, the
delayed CLKA1, CLKB1, CLKC1, and CLKD1 outputs maintain edge alignments,
phase relations, and the skews of the respective inputs.
A PMCD can be used with other clock resources including global buffers and DCMs.
Together, these clock resources provide flexibility in managing complex clock
networks in designs.
In Virtex-4 devices, the PMCDs are located in the center column.
simplified view of the Virtex-4 FPGA center column resources. The PMCDs are
grouped, with two PMCDs in one tile. The PMCDs in each tile have special
characteristics to support applications requiring multiple PMCDs.
summarizes the availability of PMCDs in each Virtex-4 device.
www.xilinx.com
Chapter 3
Figure 3-1
Table 3-1
shows a
99
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