XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 106

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2VP7-5FFG896I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC2VP7-5FFG896I
Manufacturer:
XILINX
0
Table 43: Pipelined Multiplier Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Clock to Output Pin
Setup and Hold Times Before/After Clock
Data Inputs
Clock Enable
Reset
Clock to Pin35
Clock to Pin34
Clock to Pin33
Clock to Pin32
Clock to Pin31
Clock to Pin30
Clock to Pin29
Clock to Pin28
Clock to Pin27
Clock to Pin26
Clock to Pin25
Clock to Pin24
Clock to Pin23
Clock to Pin22
Clock to Pin21
Clock to Pin20
Clock to Pin19
Clock to Pin18
Clock to Pin17
Clock to Pin16
Clock to Pin15
Clock to Pin14
Clock to Pin13
Clock to Pin12
Clock to Pin11
Clock to Pin10
Clock to Pin9
Clock to Pin8
Clock to Pin7
Clock to Pin6
Clock to Pin5
Clock to Pin4
Clock to Pin3
Clock to Pin2
Clock to Pin1
Clock to Pin0
R
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
T
T
MULIDCK_RST
MULIDCK_CE
T
MULIDCK
www.xilinx.com
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
MULTCK_P35
MULTCK_P34
MULTCK_P33
MULTCK_P32
MULTCK_P31
MULTCK_P30
MULTCK_P29
MULTCK_P28
MULTCK_P27
MULTCK_P26
MULTCK_P25
MULTCK_P24
MULTCK_P23
MULTCK_P22
MULTCK_P21
MULTCK_P20
MULTCK_P19
MULTCK_P18
MULTCK_P17
MULTCK_P16
MULTCK_P15
MULTCK_P14
MULTCK_P13
MULTCK_P12
MULTCK_P11
MULTCK_P10
Symbol
MULTCK_P9
MULTCK_P8
MULTCK_P7
MULTCK_P6
MULTCK_P5
MULTCK_P4
MULTCK_P3
MULTCK_P2
MULTCK_P1
MULTCK_P0
/T
/T
/T
MULCKID
MULCKID_CE
MULCKID_RST
0.21/–0.09
1.86/ 0.00
0.23/ 0.00
2.45
2.36
2.28
2.20
2.12
2.03
1.95
1.87
1.79
1.70
1.62
1.54
1.46
1.37
1.29
1.21
1.13
1.04
0.96
0.88
0.80
0.71
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
-7
Speed Grade
0.24/–0.09
2.06/ 0.00
0.25/ 0.00
2.92
2.82
2.72
2.62
2.52
2.42
2.32
2.22
2.12
2.02
1.92
1.82
1.71
1.61
1.51
1.41
1.31
1.21
1.11
1.01
0.91
0.81
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
0.71
-6
0.26/–0.10
2.31/ 0.00
0.28/ 0.00
3.27
3.16
3.05
2.93
2.82
2.71
2.60
2.48
2.37
2.26
2.15
2.03
1.92
1.81
1.69
1.58
1.47
1.36
1.24
1.13
1.02
0.91
0.79
0.79
0.79
0.79
0.79
0.79
0.79
0.79
0.79
0.79
0.79
0.79
0.79
0.79
-5
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
Units
35

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