XC4VFX12-12FFG668C Xilinx Inc, XC4VFX12-12FFG668C Datasheet - Page 163
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XC4VFX12-12FFG668C
Manufacturer Part Number
XC4VFX12-12FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12FFG668C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Case 5: Resetting All Flags
•
•
Clock Event 4: Read Operation and Deassertion of Read Error Signal
The read error signal pin is deasserted when a user stops trying to read from an empty
FIFO.
•
•
The read error signal is asserted/deasserted at every read-clock positive edge. As long as
both RDEN and EMPTY are true, RDERR will remain asserted.
When the reset signal is asserted, all flags are reset.
•
•
•
•
Reset is an asynchronous signal used to reset all flags. Hold the reset signal High for three
read and write clock cycles to ensure that all internal states and flags are reset to the correct
value.
At time T
RDERR output pin of the FIFO.
Data 04 remains unchanged at the DO outputs of the FIFO.
At time T
RDEN input of the FIFO.
At time T
RDERR output pin of the FIFO.
At time T
the FIFO.
At time T
output pin of the FIFO.
At time T
FIFO.
At time T
output pin of the FIFO.
AEMPTY
WRCLK
RDCLK
EMPTY
AFULL
FULL
RST
FCKO_RDERR
FCCK_RDEN
FCKO_RDERR
FCO_EMPTY
FCO_AEMPTY
FCO_FULL
FCO_AFULL
, after reset (RST), full is deasserted at the FULL output pin of the
, after reset (RST), EMPTY is asserted at the EMPTY output pin of
, after reset (RST), ALMOSTFULL is deasserted at the AFULL
, before clock event 4 (RDCLK), read enable is deasserted at the
, after reset (RST), ALMOSTEMPTY is asserted at the AEMPTY
, after clock event 3 (RDCLK), read error is asserted at the
, after clock event 4 (RDCLK), read error is deasserted at the
www.xilinx.com
Figure 4-21: Resetting All Flags
T
T
T
T
FCO_EMPTY
FCO_AEMPTY
FCO_FULL
FCO_AFULL
FIFO Timing Models and Parameters
ug070_4_21_071204
163
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