XC4VFX12-12FFG668C Xilinx Inc, XC4VFX12-12FFG668C Datasheet - Page 230
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XC4VFX12-12FFG668C
Manufacturer Part Number
XC4VFX12-12FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12FFG668C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 5: Configurable Logic Blocks (CLBs)
230
end MUX_16_1_SUBM;
architecture MUX_16_1_SUBM_arch of MUX_16_1_SUBM is
-- Component Declarations:
component MUXF7
end component;
signal DATA_MSB : std_logic;
signal DATA_LSB : std_logic;
--
begin
SELECT_PROCESS_LSB: process (SELECT_I, DATA_I)
begin
end process SELECT_PROCESS_LSB;
--
SELECT_PROCESS_MSB: process (SELECT_I, DATA_I)
begin
end process SELECT_PROCESS_MSB;
--
-- MUXF7 instantiation
U_MUXF7: MUXF7
--
end MUX_16_1_SUBM_arch;
--
);
case SELECT_I (2 downto 0) is
end case;
case SELECT_I (2 downto 0) is
end case;
when "000" => DATA_LSB <= DATA_I (0);
when "001" => DATA_LSB <= DATA_I (1);
when "010" => DATA_LSB <= DATA_I (2);
when "011" => DATA_LSB <= DATA_I (3);
when "100" => DATA_LSB <= DATA_I (4);
when "101" => DATA_LSB <= DATA_I (5);
when "110" => DATA_LSB <= DATA_I (6);
when "111" => DATA_LSB <= DATA_I (7);
when others => DATA_LSB <= 'X';
when "000" => DATA_MSB <= DATA_I (8);
when "001" => DATA_MSB <= DATA_I (9);
when "010" => DATA_MSB <= DATA_I (10);
when "011" => DATA_MSB <= DATA_I (11);
when "100" => DATA_MSB <= DATA_I (12);
when "101" => DATA_MSB <= DATA_I (13);
when "110" => DATA_MSB <= DATA_I (14);
when "111" => DATA_MSB <= DATA_I (15);
when others => DATA_MSB <= 'X';
port (
I0: in std_logic;
I1: in std_logic;
S: in std_logic;
O: out std_logic
);
port map (
I0 => DATA_LSB,
I1 => DATA_MSB,
S
O
);
=> SELECT_I (3),
=> DATA_O
DATA_O: out std_logic
www.xilinx.com
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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