XC4VFX12-12FFG668C Xilinx Inc, XC4VFX12-12FFG668C Datasheet - Page 350
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XC4VFX12-12FFG668C
Manufacturer Part Number
XC4VFX12-12FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12FFG668C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 7: SelectIO Logic Resources
350
Verilog Use Model
// Multiple instantiations of IDELAYCTRL primitives with LOC contraints
// Each instance has its own RST and RDY signal to allow for partial
// reconfiguration.
// The REFCLK signal is common to all instances (LOC and replicated
// instances)
IDELAYCTRL dlyctrl_1 (
IDELAYCTRL dlyctrl_2 (
.
.
.
IDELAYCTRL dlyctrl_n (
// The user should either declare the LOC constraints in the
// Verilog design file or in the UCF file.
// Declaring LOC constraints in the Verilog file.
// synthesis attribute loc of dlyctrl_1 is "IDELAYCTRL_X0Y0";
// synthesis attribute loc of dlyctrl_2 is "IDELAYCTRL_X0Y1";
.
.
.
// synthesis attribute loc of dlyctrl_N is "IDELAYCTRL_XnYn";
// Declaring LOC constraints in the UCF file:
INST "dlyctrl_1" LOC=IDELAYCTRL_X0Y0;
INST "dlyctrl_2" LOC=IDELAYCTRL_X0Y1;
.
.
.
INST "dlyctrl_n" LOC=IDELAYCTRL_XnYn;
// One instantiation of an IDELAYCTRL primitive without LOC constraint
// RST and RDY port signals are independent from LOC-ed instances
IDELAYCTRL dlyctrl_noloc (
www.xilinx.com
);
);
);
.RDY(rdy _1),
.REFCLK(refclk),
.RST(rst_1)
.RDY(rdy_2),
.REFCLK(refclk),
.RST(rst_2)
.RDY(rdy_n),
.REFCLK(refclk),
.RST(rst_n)
);
.RDY(rdy_noloc),
.REFCLK(refclk),
.RST(rst_noloc)
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R
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