XC4VFX12-12FFG668C Xilinx Inc, XC4VFX12-12FFG668C Datasheet - Page 38
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XC4VFX12-12FFG668C
Manufacturer Part Number
XC4VFX12-12FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12FFG668C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 1: Clock Resources
38
span half the die
All clock regions
XC4VLX15 has 8 Clock Regions
All clock regions are 16 CLBs tall
(8 CLBs up and 8 CLBs down)
Clock Tree and Nets - GCLK
Clock Regions
Virtex-4 FPGA clock trees are designed for low-skew and low-power operation. Any
unused branch is disconnected. The clock trees also manage the load/fanout when all the
logic resources are used.
All global clock lines and buffers are implemented differentially. This facilitates much
better duty cycles and common-mode noise rejection.
In the Virtex-4 architecture, the pin access of the global clock lines are not limited to the
logic resources clock pins. The global clock lines can access other pins in the CLBs without
using local interconnects. Applications requiring a very fast signal connection and large
load/fanout benefit from this architecture.
Virtex-4 devices improve the clocking distribution by the use of clock regions. Each clock
region can have up to eight global clock domains. These eight global clocks can be driven
by any combination of the 32 global clock buffers. The restrictions and rules needed in
previous FPGA architectures are no longer applicable. Specifically, a clock region is not
limited to four quadrants regardless of die/device size. Instead, the dimensions of a clock
region are fixed to 16 CLBs tall (32 IOBs) and spanning half of the die
fixing the dimensions of the clock region, larger Virtex-4 devices can have more clock
regions. As a result, Virtex-4 devices can support many more multiple clock domains than
previous FPGA architectures.
device. The logic resources in the center column (DCMs, IOBs, etc.) are located in the left
clock regions.
The DCMs, if used, utilize the global clocks in the left regions as feedback lines. Up to four
DCMs can be in a specific region. If used in the same region, IDELAYCTRL uses another
global clock in that region. The DCM companion module PMCD, if directly connected to a
global clock, will also utilize the global clocks in the same region.
8 CLBs
8 CLBs
8 CLBs
8 CLBs
Figure 1-17: Clock Regions
www.xilinx.com
Table 1-6
Center Column
Logic Resources
shows the number of clock regions in each Virtex-4
XC4VLX100 has 24 Clock Regions
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
(Figure
UG070_1_17_071304
1-17). By
R
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