XC4VFX12-12FFG668C Xilinx Inc, XC4VFX12-12FFG668C Datasheet - Page 57
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XC4VFX12-12FFG668C
Manufacturer Part Number
XC4VFX12-12FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12FFG668C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Table 2-1: Available DCM Resources
DCM Primitives
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
XC4VLX15
XC4VSX25
XC4VFX12, XC4VFX20
XC4VLX25, XC4VLX40, XC4VLX60
XC4VSX35, XC4VSX55
XC4VFX40
XC4VLX80, XC4VLX100, XC4VLX160,
XC4VLX200
XC4VFX60, XC4VFX100
XC4VFX140
R
Device
Three DCM primitives are available: DCM_BASE, DCM_PS, and DCM_ADV (see
Figure
CLKIN
CLKFB
RST
2-2).
DCM_BASE
Available DCMs
CLKFX180
CLK2X180
LOCKED
CLK180
CLK270
CLKDV
CLKFX
CLK2X
CLK90
CLK0
12
20
4
8
www.xilinx.com
Figure 2-2: DCM Primitives
Bottom Half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1
Top Half:
DCM_ADV_X0Y2, DCM_ADV_X0Y3
Bottom Half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1, DCM_ADV_X0Y2
Top Half:
DCM_ADV_X0Y3, DCM_ADV_X0Y4, DCM_ADV_X0Y5,
DCM_ADV_X0Y6, DCM_ADV_X0Y7
Bottom Half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1, DCM_ADV_X0Y2,
DCM_ADV_X0Y3, DCM_ADV_X0Y4, DCM_ADV_X0Y5
Top Half:
DCM_ADV_X0Y6, DCM_ADV_X0Y7, DCM_ADV_X0Y8,
DCM_ADV_X0Y9, DCM_ADV_X0Y10,
DCM_ADV_X0Y11
Bottom Half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1, DCM_ADV_X0Y2,
DCM_ADV_X0Y3, DCM_ADV_X0Y4, DCM_ADV_X0Y5,
DCM_ADV_X0Y6, DCM_ADV_X0Y7, DCM_ADV_X0Y8,
DCM_ADV_X0Y9
Top Half:
DCM_ADV_X0Y10, DCM_ADV_X0Y11
DCM_ADV_X0Y12, DCM_ADV_X0Y13
DCM_ADV_X0Y14, DCM_ADV_X0Y15
DCM_ADV_X0Y16, DCM_ADV_X0Y17
DCM_ADV_X0Y18, DCM_ADV_X0Y19
CLKIN
CLKFB
RST
PSINCDEC
PSEN
PSCLK
DCM_PS
CLK2X180
CLKFX180
PSDONE
LOCKED
DO[15:0]
CLK180
CLK270
CLKDV
CLKFX
CLK2X
CLK90
CLK0
Site Names
CLKIN
CLKFB
RST
PSINCDEC
PSEN
PSCLK
DADDR[6:0]
DI[15:0]
DWE
DEN
DCLK
DCM_ADV
DCM Primitives
CLK2X180
CLKFX180
PSDONE
LOCKED
UG070_2_02_080204
DO[15:0]
CLK180
CLK270
CLKDV
CLKFX
CLK2X
CLK90
DRDY
CLK0
57
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