XC4VFX40-11FFG672I Xilinx Inc, XC4VFX40-11FFG672I Datasheet - Page 36
XC4VFX40-11FFG672I
Manufacturer Part Number
XC4VFX40-11FFG672I
Description
IC FPGA VIRTEX-4 FX 40K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX40-11FFG672I
Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
352
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 1: Clock Resources
36
Additional Use Models
Asynchronous Mux Using BUFGCTRL
In some cases an application requires immediate switching between clock inputs or
bypassing the edge sensitivity of BUFGCTRL. An example is when one of the clock inputs
is no longer switching. If this happens, the clock output would not have the proper
switching conditions because the BUFGCTRL never detected a clock edge. This case uses
the asynchronous mux.
design example.
In
•
•
•
•
Figure
The current clock is from I0.
S is activated High.
The Clock output immediately switches to I1.
When Ignore signals are asserted High, glitch protection is disabled.
Figure 1-13: Asynchronous Mux with BUFGCTRL Design Example
1-14:
I1
I0
O
I1
I0
Asynchronous MUX
S
S
Figure 1-14
Design Example
Figure 1-14: Asynchronous Mux Timing Diagram
at I0
Figure 1-13
www.xilinx.com
shows the asynchronous mux timing diagram.
T
BCCKO_O
O
illustrates an asynchronous mux with BUFGCTRL
S
Begin I1
V
V
V
V
DD
DD
DD
DD
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
T
BCCKO_O
ug070_1_13_082704
UG070 (v2.6) December 1, 2008
UG070_1_14_033005
Virtex-4 FPGA User Guide
O
R
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