XC5VSX50T-2FFG665I Xilinx Inc, XC5VSX50T-2FFG665I Datasheet - Page 324
XC5VSX50T-2FFG665I
Manufacturer Part Number
XC5VSX50T-2FFG665I
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-2FFG665I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX50T-2FFG665I
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
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Chapter 7: SelectIO Logic Resources
324
Table 7-5: ILOGIC Switching Characteristics
Note:
parameters.
Setup/Hold
T
T
T
Combinatorial
T
Sequential Delays
T
T
T
T
ICE1CK
ISRCK
IDOCK
IDI
IDLO
ICKQ
ICE1Q
RQ
Symbol
The DDLY timing diagrams and parameters are identical to the D timing diagrams and
/T
/T
/T
ICKSR
IOCKD
ICKCE1
CE1 pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK
D pin to O pin propagation delay, no Delay
D pin to Q1 pin using flip-flop as a latch without Delay
CLK to Q outputs
CE1 pin to Q1 using flip-flop as a latch, propagation delay
SR/REV pin to OQ/TQ out
www.xilinx.com
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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