XCV1600E-8FG860C Xilinx Inc, XCV1600E-8FG860C Datasheet - Page 83
![no-image](/images/no-image-200.jpg)
XCV1600E-8FG860C
Manufacturer Part Number
XCV1600E-8FG860C
Description
IC FPGA 1.8V C-TEMP 860-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV200E-6CS144C.pdf
(233 pages)
Specifications of XCV1600E-8FG860C
Number Of Logic Elements/cells
34992
Number Of Labs/clbs
7776
Total Ram Bits
589824
Number Of I /o
660
Number Of Gates
2188742
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
860-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XCV1600E-8FG860C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
Notes:
1.
2.
3.
4.
5.
6.
Input Clock Period Tolerance
Input Clock Jitter Tolerance (Cycle to Cycle)
Time Required for DLL to Acquire Lock
Output Jitter (cycle-to-cycle) for any DLL Clock Output
Phase Offset between CLKIN and CLKO
Phase Offset between Clock Outputs on the DLL
Maximum Phase Difference between CLKIN and CLKO
Maximum Phase Difference between Clock Outputs on the DLL
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution, excluding
input clock jitter.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
Add 30% to the value for industrial grade parts.
R
Description
(6)
(2)
(3)
(1)
(4)
www.xilinx.com
1-800-255-7778
(5)
Symbol
T
T
T
T
T
T
T
T
PHOOM
OJITCC
PHIOM
IJITCC
PHOO
IPTOL
LOCK
PHIO
Virtex™-E 1.8 V Field Programmable Gate Arrays
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
25 - 30 MHz
> 60 MHz
F
CLKIN
CLKDLLHF
Min
-
-
-
-
-
-
-
± 150
± 100
± 140
± 160
± 200
Max
± 60
1.0
20
-
-
-
-
Min
CLKDLL
-
-
-
-
-
-
-
± 300
± 100
± 140
± 160
± 200
Max
± 60
120
1.0
20
25
50
90
Module 3 of 4
Units
ns
ps
μs
μs
μs
μs
μs
ps
ps
ps
ps
ps
23
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