XC5VFX30T-1FFG665CES Xilinx Inc, XC5VFX30T-1FFG665CES Datasheet - Page 304
![IC FPGA VIRTEX5FX 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VFX30T-1FFG665CES
Manufacturer Part Number
XC5VFX30T-1FFG665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FFG665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS non-compliant
Number Of Gates
-
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Part Number:
XC5VFX30T-1FFG665CES
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Quantity:
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Chapter 6: SelectIO Resources
304
Mixing Techniques
The connection scheme shown in
performance may be degraded by R
value and performance with an IBIS simulation.
X-Ref Target - Figure 6-93
When designing with the LVDCI_33 standard:
•
•
•
In addition, changing the slew rate from fast to slow and/or reducing the current drive
could significantly reduce overshoot and undershoot.
The Virtex-5 FPGA PCB Designer’s Guide contains additional design information to assist
PCB designers and signal integrity engineers.
Regulating V
The following section discusses alternatives for managing overshoot and undershoot for
LVTTL, LVCMOS33, and PCI applications.
When V
limits any overshoot higher than 3.5V before reaching the absolute maximum level of
4.05V. In addition, instead of –0.3V when V
corresponding to V
undershoot before reaching the lower absolute maximum limit.
As a result, lowering V
for all supported 3.3 V standards, including LVCMOS_33, LVTTL, LVDCI_33, and PCI.
Either using LVDCI_33 standard or lowering the V
address overshoot and undershoot. It is also acceptable to combine both methods. When
V
The VRP and VRN values should always be the same as the board trace impedance.
CCO
The output drive strength and slew rates are not programmable. The output
impedance references the VRP and VRN resistors, and the output current is
determined by the output impedance.
If only LVDCI_33 inputs are used, it is not necessary to connect VRP and VRN to
external reference resistors. The implementation pad report does not record VRP and
VRN being used. External reference resistors are required only if LVDCI_33 outputs
are present in a bank.
LVDCI_33 is compatible with LVTTL and LVCMOS standards only.
is lowered to 3.0V, it is not necessary to adjust the reference resistors VRP and VRN.
CCO
is lowered to 3.0V, the power clamp diode turns on at about 3.5V. Therefore it
CCO
OBUFT_LVDCI_33
IBUF_LVDCI
Virtex-5
CCO
FPGA
at 3.0V
CCO
= 3.0V is –1.05V. In this case, the ground clamp diode clips
Figure 6-93: 3.3V I/O Configuration
www.xilinx.com
to 3.0V addresses the overshoot and undershoot specifications
Figure 6-93
0
. Therefore, it is also recommended to verify the R
Z
0
CCO
is for a bidirectional bus scenario. The signal
= 3.75V, the lower absolute maximum limit
CCO
R
0
to 3.0V is a good approach to
External Device
ug190_6_87_030506
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
0
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