PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 191
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
6
5:3
2:1
0
Offset 0x04,712C
31:7
6
5:3
2:1
0
Offset 0x04,7200
31:7
6
Symbol
turn_off_ack
sel_clk_dvdd_src
sel_clk_dvdd
en_clk_dvdd
Reserved
turn_off_ack
sel_clk_dtl_mmio_src
sel_clk_dtl_mmio
en_dtl_mmio
Reserved
turn_off_ack
CLK_DTL_MMIO_CTL
CLK_QVCP_OUT_CTL
Acces
s
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
…Continued
Value
0
111
00
1
-
0
000
00
1
-
0
Rev. 4.0 — 03 December 2007
Description
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
000: clk_dvdd_src = clk_144
001: clk_dvdd_src = clk_123
010: clk_dvdd_src = clk_108
011: clk_dvdd_src = clk_96
100: clk_dvdd_src = clk_86
101: clk_dvdd_src = clk_78
110: clk_dvdd_src = clk_72
111: clk_dvdd_src = clk_54
00: clk_dvdd = 27 MHz xtal_clk
01: clk_dvdd = clk_dvdd_src
10: clk_dvdd = 27 MHz xtal_clk
11: clk_dvdd = AO_SD[2]
1: enable clk_dvdd
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
000: clk_dtl_mmio_src = clk_102
001: clk_dtl_mmio_src = clk_108
010: clk_dtl_mmio_src = clk_115
011: clk_dtl_mmio_src = clk_123
100: clk_dtl_mmio_src = clk_133
101: clk_dtl_mmio_src = clk_144
110: clk_dtl_mmio_src = clk_157
111: clk_dtl_mmio_src = clk_54
00: clk_dtl_mmio = 27 MHz xtal_clk
01: clk_dtl_mmio = clk_dtl_mmio_src
10: clk_dtl_mmio = 27 MHz xtal_clk
11: clk_dtl_mmio = AO_SD[3]
1: enable clk_dtl_mmio
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
PNX15xx/952x Series
Chapter 5: The Clock Module
© NXP B.V. 2007. All rights reserved.
5-191
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