PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 479
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Table 3: Fast general purpose output (FGPO)
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
7:5
4
3:2
Symbol
BUF_SYNC
Reserved
REC_SYNC
Acces
s
R/W
R
R/W
Value
000
0
00
Rev. 4.0 — 03 December 2007
…Continued
Description
Encodes function of fgpo_buf_sync in record mode. Encodes to
000 in message mode:
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Encodes function of fgpo_rec_sync in record/message mode.
000 = No buffer sync, ignores fgpo_buf_sync input. Switch to
alternate buffer at EOB (End-Of-Buffer). Start first buffer
immediately after OUTPUT_ENABLE_1 (bit 12 above) is set.
001 = Wait FGPO_BUF_GAP clock pulses before switch to
alternate buffer. Ignores fgpo_buf_sync input. Start first buffer
immediately after OUTPUT_ENABLE_1 (bit 12 above) is set.
010 = same as 000 above.
011 = same as 001 above.
100 = Switch buffers on rising edge on fgpo_buf_sync input.
Wait for next rising edge on fgpo_buf_sync input, after
OUTPUT_ENABLE_1 (bit 12 above) is set, to start first buffer.
101 = Switch buffers on falling edge on fgpo_buf_sync input.
Wait for next falling edge on fgpo_buf_sync input, after
OUTPUT_ENABLE_1 (bit 12 above) is set, to start first buffer.
110 = Switch buffers on alternate rising and falling edges on
fgpo_buf_sync input. Wait for next rising edge on
fgpo_buf_sync input, after OUTPUT_ENABLE_1 (bit 12 above)
is set, to start first buffer.
111 = Switch buffers on alternate edges on fgpo_buf_sync
input. Wait for next falling edge on fgpo_buf_sync input, after
OUTPUT_ENABLE_1 (bit 12 above) is set, to start first buffer.
00 = No record/message sync, ignores fgpo_rec_sync input.
Switch to next record at EOR/EOM (End-Of-Record / End-Of-
Message). Start first record/message immediately after
OUTPUT_ENABLE_1 (bit 12 above) is set.
01 = Wait FGPO_REC_GAP clock pulses before starting next
record/message. Ignores fgpo_buf_sync input. Start first
record/message immediately after OUTPUT_ENABLE_1 (bit 12
above) is set.
10 = Start record/message on fgpo_rec_sync rising edge.
11 = Start record/message on fgpo_rec_sync falling edge.
Chapter 13: FGPO: Fast General Purpose Output
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
13-479
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