PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 531
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Volume 1 of 1
3. Operation
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 2:
OSCLK
Audio In Clock System and I/O Interface
SCK
WS
SD
SD2
SD3
SD1
(e.g. 64xfs)
(e.g. 256xfs)
0
3.1.1 Clock System Operation
3.1 Clock Programming
Figure 2
is a square wave Direct Digital Synthesizer (DDS). The DDS can be programmed to
emit frequencies from approximately 1 Hz to 40 MHz with a resolution of better than
0.3 Hz. The DDS and its control registers reside in the Clocks module outside the
Audio in Unit.
The output of the DDS is always sent on the OSCLK output pin. This output is
intended to be used as the 256 f
converters.
Software may change the DDS frequency setting dynamically, so as to adjust the
input sampling rate to track an application dependent master reference. Using the
DDS function, a high quality, low-jitter OSCLK is generated.
SCK and WS can be configured as input or output, as determined by the
SER_MASTER control field. As an output, SCK is a divided form of the OSCLK
output frequency. The SCKDIV register value is used to divide down the OSCLK
frequency. See
the SCK pin signal is used as the bit clock for serial-parallel conversion. The value of
SCKDIV is determined by
Remark: SCKDIV is in the range 0-255.
f AISCK
Serial To Parallel
Converter
=
illustrates the clocking capabilities of the Audio Input unit. Driving the system
--------------------------------- -
SCKDIV
div N+1
f AIOSCLK
div N+1
SER_MASTER
Section 4. on page 16-541
Rev. 4.0 — 03 December 2007
+
1
8
7
32
32
SCKDIV
WSDIV
RIGHT0[31:0]
RIGHT1[31:0]
LEFT0[31:0]
LEFT1[31:0]
RIGHT2[31:0]
Equation
LEFT2[31:0]
LEFT3[31:0]
RIGHT3[31:0]
s
or 384 f
AI domain
12:
0
0
s
system clock source for oversampling A/D
for more details. Whether input or output,
27MHz x 64
PNX15xx/952x Series
DDS in Clocks Module
Square Wave DDS
Chapter 16: Audio Input
© NXP B.V. 2007. All rights reserved.
16-531
(12)
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