PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 815
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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7. Detailed Example
PNX15XX_PNX952X_SER_N_4
Product data sheet
The 32-bit PCI bus uses byte address conventions identical to the DTL interface and
MTL Memory Bus Interface: Refer to
Table 11: 32 Bit PCI Interface Byte Address
The DCS Network uses byte address conventions given in
The MTL Memory Bus uses the byte address conventions given in
With the above byte address conventions on the three sides of the bridge and the
byte address invariance rule for bridges, the swap modes can be derived. Since the
convention on the PCI bus closely matches those on the MTL Bus.
This section describes all steps involved in how a big-endian mode external CPU
(e.g., a Power Macintosh), paints an RGB-565 pixel format frame buffer in the
PNX15xx/952x Series SDRAM and how this is displayed on the QVCP. This example
illustrates the following:
The Power Macintosh was the first platform that successfully demonstrated big-
endian operations across the PCI bus. Details of how this works can be found in the
Apple document “Designing PCI Cards and Drivers for Power MacIntosh Computers.”
Suppose that the big-endian CPU in the Power Macintosh uses a 32-bit store
operation to create two RGB565 pixels. Pixel 1, the left-most pixel, has (byte) address
“A” and pixel 2 has address “A+2.” Since these two pixels are transferred in a single
32-bit word, “A” is a multiple of 4.
The intermediate stages that the data goes through can be found in
PCI-AD[31:24]
4n+3
•
•
•
•
•
The Power Macintosh PCI bridge and its address invariance rule based swapper
The BIG-endian PCI pixel transfer
How data arrives correct in SDRAM in native RGB565 pixel format
How the QVCP takes it and displays it
How the TM32 CPU core sees the data
Rev. 4.0 — 03 December 2007
PCI-AD[23:16]
4n+2
Table
PCI-AD[15:8]
4n+1
11.
PNX15xx/952x Series
Chapter 29: Endian Mode
Table
PCI-AD[7:0]
4n+0
8.
© NXP B.V. 2007. All rights reserved.
Table
Figure 7
9.
29-815
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