CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 12

• Manufacturer Part Number: CY7C63413C-PVXC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.25V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 1
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P02
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1852

General Purpose I/O Ports
Ports 0 to 2 provide 24 GPI/O pins that can be read or written.
Each port (8 bits) can be configured as inputs with internal
pull-ups, open drain outputs, or traditional CMOS outputs.
Please note an open drain output is also a high-impedance (no
pull-up) input. All of the I/O pins within a given port have the same
configuration. Ports 0 to 2 are considered low current drive with
typical current sink capability of 7 mA.
The internal pull-up resistors are typically 7 k. Two factors
govern the enabling and disabling of the internal pull-up
.
Table 2. Port 0 Data
Table 3. Port 1 Data
Document #: 38-08027 Rev. *E
P0[7]
P1[7]
R/W
R/W
Addr: 0x00
Addr: 0x01
P0[6]
P1[6]
R/W
R/W
Internal
Data Bus
GPIO
CFG
Interrupt
Enable
P0[5]
P1[5]
R/W
R/W
Internal
Buffer
Figure 3. Block Diagram of a GPIO Line
Port Write
Port Read
Data
Out
Latch
P0[4]
P1[4]
R/W
R/W
Port 0 Data
Port 1 Data
mode
2 bits
resistors: the port configuration selected in the GPI/O
Configuration register and the state of the output data bit. If the
GPI/O Configuration selected is “Resistive” and the output data
bit is “1,” then the internal pull-up resistor is enabled for that
GPI/O pin. Otherwise, Q1 is turned off and the 7-k pull-up is
disabled. Q2 is “ON” to sink current whenever the output data bit
is written as a “0.” Q3 provides “HIGH” source current when the
GPI/O port is configured for CMOS outputs and the output data
bit is written as a “1”. Q2 and Q3 are sized to sink and source,
respectively, roughly the same amount of current to support
traditional CMOS outputs with symmetric drive.
P0[3]
P1[3]
R/W
R/W
Q2
Q1
7 k
to Interrupt
Controller
V
CC
Q3
P0[2]
P1[2]
R/W
R/W
ESD
GPIO
Pin
P0[1]
P1[1]
R/W
R/W
CY7C63413C
CY7C63513C
CY7C63613C
P0[0]
P1[0]
R/W
R/W
Page 12 of 36
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