MM908E626AVEK Freescale Semiconductor, MM908E626AVEK Datasheet - Page 31

• Manufacturer Part Number: MM908E626AVEK
• Description: IC STEPPER MOTOR DRIVER 54-SOIC
• Manufacturer: Freescale Semiconductor
• Type: Stepper Motor Driverr

Specifications of MM908E626AVEK

• Applications: Automotive Mirror Control
• Core Processor: HC08
• Program Memory Type: FLASH (16 kB)
• Controller Series: 908E
• Ram Size: 512 x 8
• Interface: SCI, SPI
• Number Of I /o: 13
• Voltage - Supply: 8 V ~ 18 V
• Operating Temperature: -40°C ~ 115°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Product: Stepper Motor Controllers / Drivers
• Supply Current: 20 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

in the transmitter, software is advised to turn the transmitter
off immediately.
HVDD_OCF — HVDD Output Over-current Flag Bit
the HVDD pin. Clear HVDD_OCF and enable the output by
writing a logic [1] to the HVDD_OCF Flag. Reset clears the
HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no
effect.
LVF — Low Voltage Bit
Flag Register.
HVF — High Voltage Sensor Bit
Flag Register.
HB_OCF — H-bridge Over-current Flag Bit
the H-bridges. Clear HB_OCF and enable the H-bridge driver
by writing a logic [1] to HB_OCF. Reset clears the HB_OCF
bit. Writing a logic [0] to HB_OCF has no effect.
HTF — Over-temperature Status Bit
Flag Register.
AUTONOMOUS WATCHDOG (AWD)
functions:
CPU against code runaways.
Register is set. If this bit is cleared, the AWD oscillator is
disabled and the watchdog switched off.
Analog Integrated Circuit Device Data
Freescale Semiconductor
• 1 = Transmitter operating in current limitation region.
• 0 = Transmitter not operating in current limitation
This read / write flag is set on an over-current condition at
• 1 = Over-current condition on HVDD has occurred.
• 0 = No over-current condition on HVDD has occurred.
This read only bit is a copy of the LVF bit in the Interrupt
• 1 = Low voltage condition has occurred.
• 0 = No low voltage condition has occurred.
This read-only bit is a copy of the HVF bit in the Interrupt
• 1 = High voltage condition has occurred.
• 0 = No high voltage condition has occurred.
This read / write flag is set on an over-current condition at
• 1 = Over-current condition on H-bridges has occurred.
• 0 = No over-current condition on H-bridges has
This read-only bit is a copy of the HTF bit in the Interrupt
• 1 = Over-temperature condition has occurred.
• 0 = No over-temperature condition has occurred.
The Autonomous Watchdog module consists of three
• Watchdog function for the CPU in RUN mode
• Periodic interrupt function in STOP mode
The Autonomous Watchdog module allows to protect the
The AWD is enabled if AWDIE, AWDRE in the AWDCTL
region.
occurred.
Watchdog
setting the AWDRE bit, watchdog functionality in RUN mode
is activated. Once this function is enabled, it is not possible to
disable it via software.
system reset is initiated. Operations of the watchdog function
cease in STOP mode. Normal operation will be continued
when the system is back to RUN mode.
counter must be reset before it reaches the end value. This is
done by a write to the AWDRST bit in the AWDCTL Register.
PERIODIC INTERRUPT
enabled by setting the AWDIE bit in the AWDCTL Register. If
AWDIE is set, the AWD wakes up the system after a fixed
period of time. This time period can be selected with bit
AWDR in the AWDCTL Register.
Autonomous Watchdog Control Register (AWDCTL)
AWDRST — Autonomous Watchdog Reset Bit
timeout period. AWDRST always reads 0. Reset clears
AWDRST bit.
AWDRE — Autonomous Watchdog Reset Enable Bit
reset on the
Watchdog has reached the timeout and the Autonomous
Watchdog is enabled. AWDRE is one-time setable (write
once) after each reset. Reset clears the AWDRE bit.
Autonomous Watchdog Interrupt Enable Bit (AWDIE)
Autonomous Watchdog timeout flag, AWFD. IRQ_A is only
asserted when the device is in STOP mode. Reset clears the
AWDIE bit.
Notes
Reset
Read
Write
17.
The watchdog function is only available in RUN mode. On
If the timer reaches end value and AWDRE is set, a
To prevent a watchdog reset, the watchdog timeout
Periodic interrupt is only available in STOP mode. It is
This write-only bit resets the Autonomous Watchdog
• 1 = Reset AWD and restart timeout period.
• 0 = No effect.
This read / write bit enables resets on AWD time-outs. A
• 1 = Autonomous watchdog enabled.
• 0 = Autonomous watchdog disabled.
This read/write bit enables CPU interrupts by the
• 1 = CPU interrupt requests from AWDF enabled
• 0 = CPU interrupt requests from AWDF disabled
This bit must always be set to 0.
Bit 7
Register Name and Address: AWDCTL - $0a
0
0
RST_A
6
0
0
AWDRST
is asserted when the Autonomous
5
0
0
FUNCTIONAL DEVICE OPERATION
AWDRE
4
0
AWDIE
OPERATIONAL MODES
3
0
0
2
(17)
0
1
0
0
908E626
AWDR
Bit 0
0
31