EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 115

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
BRG Control Registers
UARTx_BRG_L) and outputs a pulse to indicate the end-of-count. Calculate the UART
data rate with the following equation:
Upon RESET, the 16-bit BRG divisor value resets to
value of
the Low- or High-byte registers for the BRG Divisor Latch causes both the Low and High
bytes to load into the BRG counter, and causes the count to restart.
The divisor registers can only be accessed if bit 7 of the UART Line Control register
(UARTx_LCTL) is set to 1. After reset, this bit is reset to 0.
Recommended Usage of the Baud Rate Generator
The following is the normal sequence of operations that should occur after the eZ80L92
MCU is powered on to configure the Baud Rate Generator:
•
•
•
UART Baud Rate Generator Registers—Low and High Bytes
The registers hold the Low and High bytes of the 16-bit divisor count loaded by the pro-
cessor for UART baud rate generation. The 16-bit clock divisor value is returned by
{UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two available
UART devices. On RESET, the 16-bit BRG divisor value resets to
bit divisor value must be between
invalid, and proper operation is not guaranteed. As a result, the minimum BRG clock divi-
sor ratio is 2.
A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter. The count is then restarted.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to
access this register. See
Control Registers
UART Data Rate (bps) =
Set UARTx_LCTL[7] to 1 to enable access of the BRG divisor registers
Program the UARTx_BRG_L and UARTx_BRG_H registers
Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers
0001h
is also valid, and effectively bypasses the BRG. A software Write to either
(UARTx_LCTL)
Table 52
16 x (UART Baud Rate Generator Divisor)
and
0002h
on page
Table
System Clock Frequency
and
53. For more information, see
115.
FFFFh
Universal Asynchronous Receiver/Transmitter
0002h
as the values
. A minimum BRG divisor
Product Specification
0000h
0002h
eZ80L92 MCU
. The initial 16-
UART Line
and
0001h
are
109