EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 123

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Table 61. UART Character Parameter Definition
UART Modem Control Registers
This register is used to control and check the modem status. See
Table 62. UART Modem Control Registers (UART0_MCTL = 00C4h, UART1_MCTL =
Bit
Reset
CPU Access
Note: R = Read only.; R/W = Read/Write.
Bit
Position
[7:5]
4
LOOP
CHAR[2:0]
000
001
010
011
100
101
110
111
00D4h)
Character Length
(Tx/Rx Data Bits)
Value Description
000b
0
1
Reserved.
LOOP BACK mode is not enabled.
LOOP BACK mode is enabled.
The UART operates in internal LOOP BACK mode. The
transmit data output port is disconnected from the internal
transmit data output and set to 1. The receive data input port is
disconnected and internal receive data is connected to internal
transmit data. The modem status input ports are disconnected
and the four bits of the modem control register are connected
as modem status inputs. The two modem control output ports
(OUT1&2) are set to their inactive state
5
6
7
8
5
6
7
8
R
7
0
R
6
0
(Tx Stop Bits)
Stop Bits
R
5
0
1
1
1
1
2
2
2
2
Universal Asynchronous Receiver/Transmitter
R/W
4
0
R/W
3
0
Product Specification
Table
R/W
2
0
62.
eZ80L92 MCU
R/W
1
0
R/W
0
0
117