EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 147

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
SDA Signal
SCL Signal
Transferring Data
START Condition
Byte Format
Every character transferred on the SDA line must be a single 8-bit byte. The number of
bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an
Acknowledge (ACK)
Figure
Data transfer then continues when the receiver is ready for another byte of data and
releases SCL.
Acknowledge
Data transfer with an ACK function is obligatory. The ACK-related clock pulse is gener-
ated by the master. The transmitter releases the SDA line (High) during the ACK clock
pulse. The receiver must pull down the SDA line during the ACK clock pulse so that it
remains stable Low during the High period of this clock pulse. See
A receiver that is addressed is obliged to generate an ACK after each byte is received.
When a slave-receiver doesn't acknowledge the slave address (for example, unable to
receive because it's performing some real-time function), the data line must be left High
by the slave. The master then generates a STOP condition to abort the transfer.
If a slave-receiver acknowledges the slave address, but cannot receive any more data
bytes, the master must abort the transfer. The abort is indicated by the slave generating the
Not Acknowledge (NACK) on the first byte to follow. The slave leaves the data line High
and the master generates the STOP condition.
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-
transmitter by not generating an ACK on the final byte that is clocked out of the slave. The
1. ACK is defined as a general Acknowledge bit. By contrast, the I
S
sented as AAK, bit 2 of the I
See
32. A receiver can hold the SCL line Low to force the transmitter into a wait state.
Table 84 on page 154
MSB
1
2
Figure 32. I
1
. Data is transferred with the most significant bit (msb) first. See
2
.
Acknowledge from
C Control Register, which identifies which ACK signal to transmit.
8
2
Receiver
C Frame Structure
9
1
Clock Line Held Low By Receiver
Acknowledge from
Receiver
2
C Acknowledge bit is repre-
ACK
Product Specification
9
Figure
I
2
C Serial I/O Interface
STOP Condition
33.
P
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