EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 153

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Table 77. I
When all bytes are transmitted, the processor should write a 1 to the STP bit in the
I2C_CTL register. The I
to the idle state.
Master Receive
In MASTER RECEIVE mode, the I
ter.
After the START condition is transmitted, the IFLG bit is 1 and the status code
loaded in the I2C_SR register. The I2C_DR register should be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit should be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in
I2C_SR register.
Table 78. I
Code I
30h
38h
Code
40h
Note: R = Read bit; in essence, the lsb is set to 1.
Data byte transmitted,
ACK not received
Arbitration lost
2 C State
I
Addr + R
transmitted, ACK
received
2
2
2
C Master Transmit Status Codes For Data Bytes (Continued)
C Master Receive Status Codes
C State
2
C then transmits a STOP condition, clears the STP bit and returns
MCU Response
Same as code 28h
Clear IFLG
Or set STA, clear IFLG
MCU Response
For a 7-bit address,
clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
For a 10-bit address
Write extended address
byte to DATA, clear IFLG
2
C receives a number of bytes from a slave transmit-
Next I
Same as code 28h
Return to idle
Transmit START when bus
free
Next I
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit extended
address byte
Product Specification
2 C Action
Table 78
2
I
2
C Action
C Serial I/O Interface
is in the
08h
is
147