EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 155

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
Part Number:
EZ80L92AZ050SG
Manufacturer:
Zilog
Quantity:
10 000
PS013014-0107
Note:
Table 79. I
When all bytes are received, a NACK should be sent, then the processor should write a 1
to the STP bit in the I2C_CTL register. The I
the STP bit and returns to the idle state.
Slave Transmit
In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master receiver.
The I
Read bit after a START condition. The I
bit is set to 1) and sets the IFLG bit in the I2C_CTL register and the I2C_SR register con-
tains the status code
When I
ter), it transmits an acknowledge after the first address byte is received after a restart. An
interrupt is generated, IFLG is set but the status does not change. No second address byte
is sent by the master. It is up to the slave to remember it had been selected prior to the
restart.
I
ing the transmission of an address, and the slave address and Read bit are received. This
action is represented by the status code
The data byte to be transmitted is loaded into the I2C_DR register and the IFLG bit
cleared. After the I
and the I2C_SR register contains
the I2C_DR register, the AAK bit is cleared when the IFLG is cleared. After the final byte
Code
50h
58h
38h
2
C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost dur-
2
C enters SLAVE TRANSMIT mode when it receives its own slave address and a
2
C contains a 10-bit slave address (signified by
I
Data byte received,
ACK transmitted
Data byte received,
NACK transmitted
Arbitration lost in
NACK bit
2
2
C State
C Master Receive Status Codes For Data Bytes
2
C transmits the byte and receives an acknowledge, the IFLG bit is set
A8h
.
MCU Response
Read DATA, clear IFLG,
clear AAK = 0
Or read DATA, clear IFLG,
set AAK = 1
Read DATA, set STA,
clear IFLG
Or read DATA, set STP,
clear IFLG
Or read DATA, set
STA & STP, clear IFLG
Same as master transmit
B8h
. When the final byte to be transmitted is loaded into
B0h
2
C then transmits an acknowledge bit (if the AAK
in the I2C_SR register.
2
C then transmits a STOP condition, clears
F0h–F7h
Next I
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit repeated START
Transmit STOP
Transmit STOP then
START
Same as master transmit
Product Specification
in the I2C_SAR regis-
2
C Action
I
2
C Serial I/O Interface
149

Related parts for EZ80L92AZ050SG