EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 161

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
I
The I2C_SR register is a Read-Only register that contains a 5-bit status code in the five
most significant bits: the three least significant bits are always 0. The Read-Only I2C_SR
registers share the same I/O addresses as the Write-Only I2C_CCR registers. See
Table 85. I
Bit
Position
7
IEN
6
ENAB
5
STA
4
STP
3
IFLG
2
AAK
[1:0]
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:3]
STAT
[2:0]
2
C Status Register
2
C Status Registers
Value
00
0
1
0
1
0
1
0
1
0
1
0
1
00000–11111
Value
000
R
7
1
Description
I
I
The I
ignored.
The I
Master mode START condition is sent.
Master mode start-transmit START condition on the bus.
Master mode STOP condition is sent.
Master mode stop-transmit STOP condition on the bus.
I
I
Not Acknowledge.
Acknowledge.
Reserved.
2
2
2
2
C interrupt is disabled.
C interrupt is enabled.
C interrupt flag is not set.
C interrupt flag is set.
2
2
C bus (SCL/SDA) is disabled and all inputs are
C bus (SCL/SDA) is enabled.
(I2C_SR = 00CCh)
R
6
1
5-bit I
Reserved.
Description
2
R
5
1
C status code.
R
4
1
R
3
1
Product Specification
R
2
0
I
2
C Serial I/O Interface
R
1
0
Table
R
0
0
85.
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