EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 162

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
There are 29 possible status codes, as listed in
tains the status code
ated and the IFLG bit in the I2C_CTL register is not set. All other status codes correspond
to a defined state of the I
When each of these states is entered, the corresponding status code appears in this register
and the IFLG bit in the I2C_CTL register is set. When the IFLG bit is cleared, the status
code returns to
Table 86. I
Code
00h
08h
10h
18h
20h
28h
30h
38h
40h
48h
50h
58h
60h
68h
70h
78h
80h
88h
90h
98h
A0h
A8h
Status
Bus error
START condition transmitted
Repeated START condition transmitted
Address and Write bit transmitted, ACK received
Address and Write bit transmitted, ACK not received
Data byte transmitted in MASTER mode, ACK received
Data byte transmitted in MASTER mode, ACK not received
Arbitration lost in address or data byte
Address and Read bit transmitted, ACK received
Address and Read bit transmitted, ACK not received
Data byte received in MASTER mode, ACK transmitted
Data byte received in MASTER mode, NACK transmitted
Slave address and Write bit received, ACK transmitted
Arbitration lost in address as master, slave address and Write bit received,
ACK transmitted
General Call address received, ACK transmitted
Arbitration lost in address as master, General Call address received, ACK
transmitted
Data byte received after slave address received, ACK transmitted
Data byte received after slave address received, NACK transmitted
Data byte received after General Call received, ACK transmitted
Data byte received after General Call received, NACK transmitted
STOP or repeated START condition received in SLAVE mode
Slave address and Read bit received, ACK transmitted
2
C Status Codes
F8h
.
F8h
, no relevant status information is available, no interrupt is gener-
2
C.
Table
86. When the I2C_SR register con-
Product Specification
I
2
C Serial I/O Interface
156