EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 163

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Note:
Table 86. I
If an illegal condition occurs on the I
00h
IFLG bit cleared. The I
on the I
The STP and STA bits may be set to 1 at the same time to recover from the bus error. The
I
I
The I2C_CCR register is a Write-Only register. The seven LSBs control the frequency at
which the I
is in MASTER mode. The Write-Only I2C_CCR registers share the same I/O addresses as
the Read-Only I2C_SR registers. See
Table 87. I
Code
B0h
B8h
C0h
C8h
D0h
D8h
F8h
Bit
Reset
CPU Access
Note: W = Read only.
Bit
Position
7
2
2
C Clock Control Register
C then sends a START.
). To recover from this state, the STP bit in the I2C_CTL register must be set and the
2
C bus.
2
Status
Arbitration lost in address as master, slave address and Read bit received,
ACK transmitted
Data byte transmitted in SLAVE mode, ACK received
Data byte transmitted in SLAVE mode, ACK not received
Last byte transmitted in SLAVE mode, ACK received
Second Address byte and Write bit transmitted, ACK received
Second Address byte and Write bit transmitted, ACK not received
No relevant status information, IFLG = 0
2
2
C bus is sampled and the frequency of the I
C Status Codes (Continued)
C Clock Control Registers
2
C then returns to the idle state. No STOP condition is transmitted
Value
0
W
7
0
W
6
0
Description
Reserved.
2
Table
C bus, the bus error state is entered (status code
W
87.
5
0
(I2C_CCR = 00CCh)
W
4
0
2
C clock line (SCL) when the I
W
3
0
Product Specification
W
2
0
I
2
C Serial I/O Interface
W
1
0
W
0
0
2
C
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